- Play a role in definition and FPGA implementations of high-performance image/video processing pipelines
- Collaborate with other experts in imaging to craft the best trade-offs in resources, cost, performance, and practicality to create optimal video processing architectures
- Work with other contributors in the FPGA space to harmonize the video processing implementation with established best practices
- Implement designs using (System)Verilog and C/C++ (High Level Synthesis)
- Verify implemented designs in simulation and on hardware
- Collaborate on improvements to FPGA design and verification methodology; investigate new technologies that would reduce development / verification time
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FPGA Engineer Video
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Senior FPGA Engineer
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FPGA Engineer
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Senior FPGA Engineer
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FPGA Verification Engineer
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Senior FPGA Engineer
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Intuitive Surgical Sunnyvale, United States OTHERJob Description · Reporting to the Manager of FPGA – Imaging, this Engineer will play a role in delivering best-in-class image/video processing solutions for our da Vinci systems, as part of a strong cross-functional team. The engineer in this position will work with the broader ...
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Software Engineer, FPGA Automation, Kuiper
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FPGA Engineer - Sunnyvale, United States - Intuitive Surgical
Description
Job Description
Reporting to the Manager of FPGA – Imaging, this Engineer will play a role in delivering best-in-class image/video processing solutions for our da Vinci systems, as part of an excellent cross-functional team. The engineer in this position will work with the broader Vision and EE teams to architect, implement and verify image sensor interfaces and image processing algorithms on FPGAs deployed on the platform. This includes components in the entire processing chain, photon-to-photon: from image sensor data acquisition to stereo (and mono) displays.
The ideal candidate will possess a proven background in FPGA-based video/image processing with exposure to typical image processing algorithms and image sensor interfaces – implementation and evaluation with the trade-offs between visual quality, performance, and FPGA resource utilization in mind.
Responsibilities