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    CPU Core Formal Verification Eng - Boise, United States - Idaho State Job Bank

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    CPU Core Formal Verification Eng at Intel in Boise, Idaho, United States Job Description Job Description Performs functional verification of CPU logic to ensure design will meet specification requirements.

    Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.

    Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.

    Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests.

    Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

    Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of architecture and microarchitecture features of the CPU being designed actively. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


    Minimum Qualifications:
    Candidate must have a Bachelors degree in Computer Engineering or Electrical Engineering and 3+ years of relevant work experience - OR - a master's degree in computer engineering or electrical engineering and 2+ years with relevant work experience


    2+ years' experience in/with:

    In-depth computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management Industry standard formal verification tools such as JasperGold, IFV, Questa Formal, VC Formal Applying sequential equivalence checking in complex micro-architectures Formal abstractions and other complexity reduction techniques.

    Hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools Assertion writing, checker development, coverage analysis, failure debug, root cause analysis Programming in at least one language:
    C/C++, Java, Specman E etc and familiarity with any of scripting languages: Perl, Python, Ruby, TCL Intel or industry experience in pre-silicon verification of CPU cores, including specific areas of technical ownership/expertise relevant to CPUs Preferred E To view full details and how to apply, please login or create a Job Seeker account