DV Engineer Wanted for Emulation and Simulation Tasks - San Diego - beBeeDesignVerification

    beBeeDesignVerification
    beBeeDesignVerification San Diego

    1 day ago

    Job title: Senior Design Verification Engineer

    Description

    DV Engineer Wanted for Emulation and Simulation Tasks

    This role requires a highly skilled engineer to develop and own end-to-end DV tasks from coding Test benches and test cases, writing assertions, running simulations, and achieving all coverage goals. The ideal candidate should have a strong background in RTL design, Verilog, and System Verilog, as well as experience with ASIC design, verification, validation, integration, or related work experience.

    Job Summary:

    • This role involves developing and implementing verification methodology to ensure scalability and portability across simulation and emulation
    • Familiarity with RTL design in Verilog and System Verilog
    • Developing test plans to verify hardware building blocks, design macros, and standard interfaces
    • Owning end-to-end DV tasks from coding Test benches and test cases, writing assertions, running simulations, and achieving all coverage goals

    A strong understanding of chip-level functional model building, OOP concepts, and HVL such as System Verilog, UVM/OVM & System C is required. Additionally, knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc. is a plus.


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