FPGA/RTL Design Engineer - Santa Clara
2 weeks ago

Key responsibilities include participating in product development cycle, designing high-performance logic using SystemVerilog/Verilog,
utilizing Vivado and Vitis ecosystems to integrate custom IP with Network on Chip (NoC), memory,
and other subsystems;
Pre-Silicon Verification:,. Qualifications: strong background in RTL design
& FPGADevelopment; hands-on experience with Vivado,Vitis,and relevant scripting languages TCL
& Python;Familiaritywith high-speed interfaces PCIe,CXL,Ethernet,
Dexian is an Equal Opportunity Employer that recruits
& hires qualified candidates without regard to race religion sex sexual orientation gender identity age national origin ancestry citizenship disability or veteran status.
Job description
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