Physical Design Flow and Methodology Engineer - Sunnyvale, CA

We are a leading company in the semiconductor industry driving innovations that shape our lives and connections. We are seeking a visionary engineering leader to lead our R&D teams and deliver cutting-edge solutions at scale. · ...

+Job summary · Join the Chip Innovation Infrastructure team to engineer the future of ASIC design at Google. · +Architect and implement next generation Physical Design EDA CAD tool workflows for ASIC development. · Collaborate with chip design teams to implement tools and methodo ...

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. · ...

We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way.Our employees are not only part of history, they're making history. · Possess devises and implements methods and procedures for inspecting t ...

We are seeking an ASIC Power Engineer to perform power analysis and optimizations in ASIC for Client AR/VR products. The ideal candidate will have experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules). Primary languages are Python and SystemVeril ...

Leads hands-on power analysis and validation for wearable devices ensuring system power behavior meets performance reliability and safety expectations. · Executes detailed electrical measurements troubleshooting and system-level analysis with strong emphasis on direct testing and ...

We are seeking a Physical Design Engineer with strong technical skills in digital implementation and optimization. · Execute RTL-to-GDSII digital implementation flows, including logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off quality c ...

This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment, utilizing Google labs, power, and safety equipment. · ...

We are looking for a User Study researcher. · 3+ years of industry experience in one or more of the following fields/roles: Operations (i.e. data, product, lab, R&D etc.) Test/Quality/Support Engineering or Technical Program Management · ...

In this role, you'll work to shape the future of AI/ML hardware acceleration. · ...

This would be a Full Time opportunity to perform power analysis and optimizations in ASIC for Client's AR/VR products. · ...

ASIC Power Engineer to perform power analysis and optimizations in ASIC for Client's AR/VR products. · Perform PPA optimization with Fusion compiler. · Perform RTL and netlist level Power analysis. · ...

This is a specialized role which requires physical interaction with hardware equipment in simulated data center environment utilizing Google labs power safety equipment. · Collaborate on data center hardware platforms across wide range of domains including semiconductors test Per ...

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. · ...

A privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical l ...

We are looking for an ASIC Power Engineer to perform power analysis and optimizations in ASIC for Metas AR/VR products. · ...

Lead micro-architecture exploration and development of complex ASIC blocks and subsystems targeting data-center applications including ML network acceleration video transcoding. · ...

This role will work to shape the future of AI/ML hardware acceleration by developing custom silicon solutions that power Google's most demanding AI/ML applications. · ...

We are seeking a highly experienced ASIC Power Engineer to support power analysis and optimization for next-generation AR/VR silicon products. · Perform ASIC power analysis and optimization at RTL and gate-level (netlist) · Drive PPA optimization using Synopsys Fusion Compiler · ...

This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment utilizing Google labs power and safety equipment. Regular development and processing of engineering hardware must be performed on site. ...