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    Design Verification Engineer - Austin, United States - Mastech Digital

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    Description

    Job Title :
    Design Verification Engineer

    Location:
    Austin, TX

    Requirements


    • 5-15 year's industry experience in a design verification role.
    • Proficient in System Verilog/UVM/OVM, OOP/C++
    • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
    • Experience with code coverage and functional coverage driven verification methodology.
    • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.
    • Excellent working knowledge of scripting languages such as Python or Perl.
    • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
    • Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
    • Strong debugging skills
    • Strong programming skills with good understanding of algorithms and data structures
    • Good verbal and written communication skills.

    Recruiter Name:
    Divya Mishra


    Recruiter Phone:
    or


    Recruiter Email Id :
    Equal Employment Opportunity
    #Mastech1

    #J-18808-Ljbffr


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