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    Principal Physical Design Engineer - Portland, United States - Microsoft Corporation

    Microsoft Corporation
    Microsoft Corporation Portland, United States

    1 week ago

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    Description
    Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world.

    Microsofts Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

    We are looking for a Principal Physical Design Engineer to work on industry-leading, high-speed, mixed-signal interface IP development as part of the SCIPS (Semi-custom and Central IP Silicon) team.

    The candidate should be a motivated self-starter with the ability to lead others who will thrive in this cutting-edge technical environment.

    Microsofts mission is to empower every person and every organization on the planet to achieve more.

    As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals.

    Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

    Were committed to a diverse and inclusive workplace and encourage applicants from all background and walks of life. Difference makes us better. Required Qualifications9+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experienceOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experienceOR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.9+ years of experience in hardware design.6+ years of experience in RTL-to
    • GDS tasks such as floorplanning, bump planning, synthesis, timing closure, place and route, electromigration & voltage drop, and physical verification.
    Other RequirementsAbility to meet Microsoft, customer and/or government security screening requirements are required for this role.

    These requirements include, but are not limited to the following specialized security screenings:

    Microsoft Cloud Background Check:
    This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

    Additional or Preferred Qualifications15+ years technical engineering experienceOR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experienceOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experienceOR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experienceExperience with Fusion Compiler, Primetime, Redhawk, Calibre, STAR-RCXT.Experience with PD for multiple clock and voltage domains IPs or subsystems.

    Experience integrating analog designs with digital, as part of a mixed-signal IP or subsystem.
    Experience in SoC-level PD, including bumps, capacitors, ESD.Experience in recent synthesis tool capabilities and methods for PPA improvement.
    Experience in PD signoff for timing, electromigration, and voltage drop.
    Tcl, Perl, Python, shell programming.
    Experience providing technical direction to less-experienced PD engineers.
    Experience leading and delivering large subsystems or SoCs.
    Experience providing status and presenting risk mitigation options to upper level management.
    Silicon Engineering IC
    • The typical base pay range for this role across the U.
    S. is USD $133,600 - $256,800 per year.

    There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.

    Certain roles may be eligible for benefits and other compensation.

    Find additional benefits and pay information here:
    Microsoft will accept applications for the role until May 6, 2024.Microsoft is an equal opportunity employer.

    All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

    We also consider qualified applicants regardless of criminal histories, consistent with legal requirements.

    If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

    Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

    Working alongside IP architects and circuit designers to develop solutions that meet system-on-a-chip (SoC_ team requirements.

    Being responsible for all aspects of physical design including floorplanning, bump and ESD planning, synthesis, place-and-route, clock tree synthesis (CTS) and signoff for timing, electromigration & voltage drop, and physical verification.

    Integrating complex analog IPs within a digital system. Being a key interface between IP and SoC. Working with packaging engineers to understand IP requirements for 2D, 2.5D and 3D packaging options. Communicatiing to coordinate and drive collaboration with RTL, DFT, CAD and SoC teams. Provide technical direction to less-experienced physical design engineers.
    Work with limited direction and have attention to detail.
    Provide crisp status of progress, issues, and risks on the program to the management team.
    Embody our culture and values.
    Employment typeFull-TimeWork siteUp to 50% work from homeRole typeIndividual ContributorDisciplineSilicon EngineeringProfessionHardware Engineering
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