FPGA Digital Design Engineer with Security Clearance - San Francisco, United States - The Computer Merchant, Ltd.

Description

• The selected candidate for the FPGA Digital Design Engineer must have 4+ years detailed electronics design experience with at least 4 years of FPGA design experience (verification experience is a plus).
• We value enthusiasm and dedication toward developing highly integrated CubeSat and Blue Canyon Technologies FPGA design solutions and products
• Candidates must be U.S. Citizens with a Bachelors Degree

• BS degree or higher in Electrical Engineering
• Experience with design trades, design concept discussions, system specifications, system analyses and failure reporting.
• Exceptional written communication skills, strong presentation skills and the ability to contribute to technical group discussions and conversations with customers and team members
• Engineers who are interested in working on a small team of enthusiastic technical experts are encouraged to apply. This opportunity includes close mentorship with a technical expert
• Familiarity with clock domain crossing (CDC) tools and FPGA design pitfalls is nice to have.
• Familiar with AXI based design, DMA, and scripting tools.
• Experience with interpreting schematics, using schematic capture tools, and digital board design is a plus.
• Experience with embedded processor-based electronics architecture.
• Strong interpersonal and self-leadership skills. We have a great team Blue Canyon values people skills and technical competence working together.
• Related technical experience may be considered in lieu of education

• Works independently and with limited supervision to generate FPGA designs based on detailed design requirements using primarily VHDL
• Design and verify margin, compliance, and fault robustness of high-speed serial interfaces such as 10 Mb /100Mb/1Gb Ethernet, SpaceWire and LVDS interfaces using simulation methods such as UVM, OVM, or a functional test bench (module and system level)
• Capture requirements, create state diagrams, timing diagrams, and other design documentation as required by the design process
• Design robust Finite State Machines (FSMs) and interface logic
• Generate FPGA test vectors and simulation test benches, executing them in a verification environment such as ModelSim or QuestaSim
• Develop constraints for and synthesize FPGA designs using Client, Libero, Libero SoC, and Vivado tool suites
• Capable of chip-level and board-level debug in the lab with a variety of test equipment with supervision as needed
• Communicates design detail, issues, and concerns effectively in verbal and written form.
• Other responsibilities as assigned.