- Work within a multi-discipline team of engineers to design Software Defined Radios (SDRs), On-Board Processors (OBPs) and storage solutions for space applications utilizing the latest Xilinx technologies (e.g., Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, and the VERSAL ACAP)
- Create and maintain complete FPGA designs using a combination of VHDL and Vivado IP Integrator with a strong emphasis on efficient data path architecture, reliable timing closures, and high-performance implementations
- Code, simulate, and verify a wide range of RTL modules for FPGAs including modules for digital signal processing (DSP), control algorithms, interfaces to external peripherals, etc.
- Design and implement solutions that use embedded ARM processors, DDR4 memories, high-speed serial interfaces such as Aurora, JESD204B/C, PCIe, 1G/10G/40G Ethernet, etc.
- Create and maintain comprehensive simulation test bench modules to ensure a high degree of code coverage and verify functionality of firmware modules
- Create and maintain Timing Constraints to ensure design is fully constrained and consistent Timing Results are achieved post-implementation
- Create and maintain Core Level and Top-Level design documents
- Participate in code reviews, design reviews, and contribute towards FPGA Design methodologies and best practices
- Work in close collaboration with hardware and software engineers throughout the integration process to ensure that FPGA designs are correctly implemented
- Thorough understanding of FPGA design methodologies including physical synthesis, static timing analysis, formal verification, power analysis, and other DRC centric tools
- Experience working with Xilinx FPGAs and the Vivado Design Suite
- Experience writing simulation testbenches to identify bugs and verify designs
- Experience using Modelsim/Questasim and/or Aldec simulation tools
- Experience using simulation verification libraries such as UVVM, UVM, OVM, etc.
- Experience writing constraints for timing verification
- Experience with board bring-up/verification in an electronic lab environment
- Familiarity with lab test equipment such as logic analyzers, oscilloscopes, signal generators, spectrum analyzers, etc.
- Experience using revision control systems, such as Git
- Must be a highly productive, self-motivated person able to contribute as an individual and work within a distributed team
- Ability to train and mentor junior engineers
- Must possess very good communication skills, verbal and written
- Ability to be granted a security clearance
- MATLAB and Simulink
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Senior FPGA Engineer - Fairfax, United States - Trident Systems
Description
Full Time Employee Full-TimeProfessional
Fairfax, VA, US
At Trident Systems' Space Electronic Systems (SES) division, we believe in the power of using strong engineering principles to drive innovation and solve complex problems.
We foster a culture of rigorous engineering and continuous improvement, leveraging the full knowledge of our organization through collaborative development processes that include design and peer reviews.
We combine our expertise in space electronics with right-sized development processes to create innovative, high-performance space-based electronic systems that meet our customers' evolving needs.
We are a mission partner supporting DoD, Intelligence, and Civil space customers.We develop complex radiation effects mitigated designs that balance competing requirements in modern space programs, delivering cutting-edge solutions that enable our customers to achieve more in space.
Mentor junior engineers:
provide training, guidance, and support as needed
Knowledge, Skills & Abilities:
Required:
Preferred Experience:
EEO Statement:
All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of disability,
race, national origin, color, religion, sex,
gender identity, or sexual orientation.
Trident Systems Incorporated is an Equal Opportunity Employer of protected Veterans and a VEVRAA Federal Contractor. Trident Systems has a desire for priority referrals of protected Veterans.
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