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Design Verification Engineer - El Segundo, United States - Acl Digital
Description
Role:
Sr. UVM Design Verification Engineer (ASIC/FPGA)
Location:
El Segundo, California (Onsite)
Duration:
ContractDescription:ASIC/FPGA Design Verification Engineer with UVM ExperienceMust have min 5 years of experience, UVM experience is important and required
Required Skills:
5+ years of experience 1-2 years of UVM tool Cadence Xcelium verification toolEducation:Must have a Bachelors Degree in Engineering.
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