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- Expertise in developing, implementing and verifying STA constraints
- Expertise in efficient closure of Subsystem as well as SoC-level timing
- In-depth knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
- Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes
- Contribute to timing flow and methodology improvements
- Collaborate with members of a global design team to complete large SoC (system-on-chip) projects.
- Demonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designs.
- Understand crosstalk, noise, OCV, timing margins. Familiarity with Clock specs, jitter, IR drop, spice analysis.
- Working with multi-site teams for execution
- Work with methodology teams to constantly improve flows and processes
- MS in Electrical or Computer Engineering
- 10+ years of experience in Physical Design
- Experience with STA Lead roles
Senior Principal Static Timing Analysis Engineer, SOC-Implementation - Austin, United States - NXP Semiconductors N.V.
Description
Timing Analysis activities for MCU/MPU SoC's.NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.