- Ownership for chip/system level architecture models at the performance and functional level (device/block C/C++ models, ns3 models). Own device architecture validation, device-level optimizations, feasibility proof, functional interaction and correctness with system software and networking stacks.
- Ownership for equivalence methodology to RTL with a view into architecture/design co-verification.
- Ownership of device and system fitness for large-scale distributed applications such as deep learning.
- Ownership of key areas of chip-level architecture definition and implementation details, working from high-level concepts/problems/specifications and customer inputs.
- Develop and maintain the simulation methodology for performance modeling for the device architecture including queueing & packet processing models. Incorporate functional models into performance models.
- Own coding of the models in C/C++ and roadmap/strategy/interlocks for model development. Produce detailed documentation for the models, including pseudo-code and equivalence checking to RTL.
- Fully specify the methodology and software required to exercise the models; log results, perform regression testing, or correlate against functional and RTL DV simulations.
- Drive product architecture definition, tradeoffs, and validation in new areas/directions, including network / system / I/O virtualization, security, root of trust, system/board management.
- Leverage simulation efforts for customer validation by adjusting the model to per-customer variants, drive evolution of the models to achieve both customer and internal development goals.
- Create specifications for software and for microarchitecture teams, and collaborate closely with both teams towards meeting aggressive product specifications and schedules.
- Drive innovations at the system and chip level to address technical challenges in front of the company.
- Significant experience in processor or networking chip architecture definition, modeling and/or validation at an industry or product category leader.
- Must have coded and validated silicon/system behavioral models in C, systemC, or C++; experience with ns3 or other multi-node network simulators a plus.
- Hands-on knowledge and/or programming experience with distributed cluster-scale applications.
- Track record of successful involvement in infrastructure product execution/deployment.
- Solid programming skills in C/C++; fluency in scripting languages (Python, Perl) desired.
- Understanding of silicon chip architecture and fundamentals required; proficiency in Verilog/SystemVerilog and testbench creation a plus.
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System and Chip Simulation Engineer - Mountain View, United States - Enfabrica
Description
Job Description
Job DescriptionSYSTEM ARCHITECT - MODELINGWe are looking for an infrastructure-savvy System Architect who comprehensively understands both large-scale distributed systems and networking silicon design, and is able to specify, model, and simulate silicon chip and system level behavior to advance the definition of a breakthrough category-defining infrastructure networking product.
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