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Principal/Senior Staff/Staff GPGPU Design Engineer - San Francisco, CA, United States - SQL Pager LLC
Description
Principal/Senior Staff/Staff GPGPU Design Engineer Client Overview Client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, it is targeting best in class latency with order of magnitude improvements for years to come. Low Latency has become the key enabler for the niche and other real-time application and the current industry' state-of-the art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC, to deliver unrivaled products to mission-critical and real-time applications. This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellency. You'll have relentlessly high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve our products' performance, quality and cost. We're changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm. Job Responsibilities•We are seeking a dedicated hands-on GPGPU Design Engineer to help develop an GPGPU for our artificial intelligence computing architecture
•As a Design Engineer, you will be participating in Architecture definition and modeling, verification test plan and testbench architecture.
•You will be responsible for developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.
•Collaborate with Algorithm and Verification teams to design various functional IPs in RISC-V based complex SoC.
•Define a micro-architecture for the implementation and the usage of the functional block IP, possibly with external sourced IPs.
•Participate SoC level integration and verifications.
•Work with the Physical design team for the timing closure Required Skills 10+years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of general experience as an GPGPU Digital Design Engineer.
•Experience in converting a module-level micro-architecture definition from given Marketing requirements.
•Expert in RTL Logic Design, CDC, RDC, Scan insertion, Lint, LEC., and synthesis with timing constraints.
•Experience in low-power design with UPF.
•Scripting experience with Tcl, Python (or similar) language. At least gone through entire ASIC design phases; from micro-architecture to post-silicon bringing-up, and validation. In-depth Knowledge of one of the parallel processing hardware architectures
•Neural Network Computation Flow on GPU/NPU
•Array/Vector/Systolic Processors
•SIMD/SIMT Processing Pipelines
•Base Jump manycore
•GPU cache hierarch and Latency-hiding with NoC Inter-connect bus fabric Nice to have Prior experience of a GPU functional blocks, including Caches
Knowledge in various DNN networks and their core ASIC implementations
Knowledge of Graphics/Compute APIs, such as CUDA/OpenCL
Knowledge of OS, software/hardware interface
Finite Precision Analysis of multi-layer compute processing pipeline Education BSEE/BSCE or equivalent.
Master's degree in science is preferred, but not required.
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