Lead Design Verification Engineer - San Jose - SQL Pager LLC

    SQL Pager LLC
    SQL Pager LLC San Jose

    3 hours ago

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    Description

    Job Summary

    A full-time, direct-hire role at a leading semiconductor company seeks an experienced Design Verification Engineer to lead verification efforts on PCIe IPs and SoC products.

    Key Responsibilities

    • Architect and build system and unit-level UVM verification environment
    • Work with architects to define verification strategy and execution plans
    • Review metrics and deliver tasks with high quality
    • Analyze Functional, Code, and Test Plan Coverage
    • Drive and participate in Code Reviews
    • Identify, drive, and develop efficiency and IP quality improvement initiatives
    • Drive root cause analysis and corrective actions for Functional bugs found in Silicon
    • Drive projects from start to finish and conduct Design verification sign-off

    Qualifications

    To be successful in this role, candidates should possess:

    • Masters degree in Electrical Engineering or related field
    • 5 years of industrial experience in Design Verification
    • Proficiency in SystemVerilog and Object-Oriented Programming
    • Experience in UVM, SVA, VIP, DPI
    • Understanding of verification best practices
    • Experience in PCIe protocol stack
    • Proficient scripting language in one of: Python, TCL, Shell, Perl
    • Self-motivated team worker

    PREFERRED QUALIFICATIONS

    • Overall design verification experience in the ASIC industry
    • Design verification lead or management experience
    • Strong background in development of verification environments in System Verilog
    • Expertise in constrained random verification methodologies
    • Formal verification experience
    • Extensive experience verifying complex designs using UVM
    • Experience in CXL, AXI, AHB, USB, I2C, Ethernet


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