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    Senior Design Verification Engineer - Redmond, United States - Microsoft Corporation

    Microsoft Corporation
    Microsoft Corporation Redmond, United States

    3 weeks ago

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    Description
    Microsofts mission is to empower every person and every organization on the planet to achieve more. Join us to achieve this by building the worlds computer.

    The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible.

    We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.

    We are looking for a Senior Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team.

    The candidate be a highly motivated self-starter who will thrive in this cutting-edge technical environment. You will be part of the design verification team, driving many facets of high performance, high bandwidth designs.

    Required Qualifications7+ years of related technical engineering experience Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experienceOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science,or related field AND 3+ years technical engineering experienceOR internship experience Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science7+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals, testbenches, stimulus generation7+ years of experience in debugging RTL (Verilog) designs as well as simulation and/or emulation environments3+ years of experience with scripting languages such as Python or Perl or shell scripts.


    Other Requirements:
    Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.

    These requirements?include, but are not limited to the following specialized security screenings:

    Microsoft Cloud Background Check:

    This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.?Preferred Qualifications10+ years of technical engineering experienceOR Bachelor's degree in Electrical Engineering, Computer Engineering, or related field AND 8+ years of technical engineering experienceOR Master's degree in Electrical Engineering, Computer Engineering, or related field AND 6+ years of technical engineering experienceOR Doctorate degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience.10+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification FundamentalExperienced in test plan development to define test cases, checkers, assertions, and functional coverage points.

    Experience in verification of many designs at unit level.
    Knowledge of verification principles, testbenches, UVM, and coverage.
    Knowledge of system verilog class, constraints, coverage and assertions.
    Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
    Proficient in reading, debugging, and/or designing using Verilog languagesSilicon Engineering IC
    • The typical base pay range for this role across the U.
    S. is USD $112,000 - $218,400 per year.

    There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.

    Certain roles may be eligible for benefits and other compensation.

    Find additional benefits and pay information here:
    Microsoft will accept applications for the role until April 30, 2024.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

    Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

    Define verification strategy, requirements, test environments for IP level verification.
    Create testplans and write tests to provide complete features coverage.

    Own verification for complex IPs, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.

    Develop and implement technical solutions to complex quality and design challenges.
    Write scoreboards, sequences, constraints, assertions and functional coverage.
    Write makefiles and scripts for verification infrastructure.
    Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
    Lead small teams of verification engineers and mentor engineers.
    Collaborate with teams across sites and geographies. Employment typeFull-TimeWork siteUp to 50% work from homeRole typeIndividual ContributorDisciplineSilicon EngineeringProfessionHardware Engineering
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