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- Significant UVM SystemVerilog experience in complex test-benches
- Experience working with DRAM controller PHYs memory models is preferred
- Significant experience with general verification flows and metrics
- Excellent debug skills
- Working with big teams across multiple geographiesEXPERIENCE AND EDUCATION
- 7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
- Strong Verilog/System Verilog knowledge
- Has developed or significantly changed components in UVM testbenches - monitors / checkers / sequences
- Some experience with SVA or formal are preferred.
- Ability to debug design/TB failures using logfiles and waveforms
- Knowledge of scripting language (PYTHON or PERL)
- Strong analytical skills and attention to detail;
- Strong written and communication skills
Verification Engineer - Santa Clara CA, United States - Cynet Systems Inc
