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- CPU environmentsIn depth understanding of networking standards, bus protocols, high speed serial link protocolsExperience with CPU instruction set testing and cache coherent system testingKnowledge of verification IP and functional coverage techniquesExperience with gate level simulations of delay annotated netlistsExposure to FPGA emulation and lab validationProject planning and execution and performing test strategy tradeoffs to achieve coverage and schedule targetsStrong leadership and experience building world class verification teamsBS in Electrical Engineering or related +13 years of experience, or MS +11 years of experience, or Ph.
Senior Design Verification Engineer - Carlsbad, United States - ASICSoft
ASICSoft
Carlsbad, United States
3 weeks ago