Elect Design and Analy Engr 3 - El Segundo, CA, United States - The Judge Group

Description

Our client is currently seeking a Elect Design and Analy Engr 3
Duration: 6 months (Manager highly likely to consider extending contract or converting the right candidate in future.)

Work Location:
El Segundo CA 90245

OnsiteJob Description:

Title:
ASIC/FPGA Design Verification Engineer with UVM ExperienceCreate UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases.
Verify until functional coverage and code coverage meet project threshold


Document resultsRequired Skills:

• 5+ years of experience
• 1-2 years of UVM tool

Cadence Xcelium verification toolEducation:
Must have min Bachelor's in Engineering (no exception, please do not submit candidates without)

Additional Details:

Must have min 5 years of experience, please do not submit without, manager will reject (he's interviews are thorough and so is his resume review, please thorough screen candidates).

UVM experience is important and required. Manager highly likely to consider extending contract or converting the right candidate in future.
Successful completion of training is a contingency for this assignment - OJT or formal classroom trainingEducation / Experience:Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g.

Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g.

PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.