- BS in material / mechanical / electrical engineering. Master's degree in engineering is preferred.
- Minimum of 3 years of experience executing semiconductor package NPI including package co-design, BOM definition, Flip-chip package technology, OSATs subcontractor management, package qualifications of component and board level, failure analysis, and electrical/thermal/mechanical interactions.
- Proven track record defining package BOM that enable device features creating value for customers. Understanding of package technologies, working with leading OSATs through the design manufacturing, qualification and release to production.
- Entrepreneurial, open-mind behavior and hands-on work ethic with the ability to prioritize a dynamic list of multiple tasks. Working with minimal guidance and supervision to deliver solutions. Quality mindset putting the silicon health at the center of all development activities.
- Deep understanding of FCCSP and FCBGA packages from perspectives of material characteristics, manufacturing, BOM, performance, supply chain, reliability, risk management and failure analysis.
- Working knowledge of SERDES package FOM such as material, thermal and mechanical performance, signal and power integrity, manufacturing risks, yield, etc. Able to deliver package solution within given specs and cost/manufacturability boundary. Work cross-functionally both internally and externally.
- Proven track record of analyzing Electrical and package level reliability tests, including HAST, HTOL, ESD, Temperature cycle, dynamic warpage, CLR and BLR.
- Ability to perform and interpret both destructive and non-destructive package failure analysis such as CSAM/TSAM/X-ray/ball-shear/SEM, to assess package reliability.
- Close interfacing with OSATs and material partners, to develop and bring up new packaging technology from definition to prototyping and mass production, using industry standard qualification processes.
- Allegro Package Designer (APD) experience for design verification for sign-off, generating reports and simple design changes.
- Broad packaging experience for example - heterogeneous packaging, flip-chip panel level designs, wafer level packaging.
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Packaging Engineer - San Jose, United States - InterSources
Description
Title: Packaging Engineer (Semiconductor)
Location: Santa Clara, CA
Duration: Full-time/Perm
Client Labs Inc., a semiconductor company headquartered in the heart of California's Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Client Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company's product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
As an Client Labs Semiconductor Packaging Engineer, you will be part of the packaging team that develops Client Labs' portfolio of connectivity products in the world's leading cloud service providers and server and networking OEMs. In this role, you will need to execute on package engineering deliverables during product definition, development, qualification, initial ramp, and high-volume production. You will work closely with chip & package design, Flip Chip assembly & manufacturing, and product & quality engineering to meet program expectations including schedule, cost, manufacturability, signal integrity, mechanical and thermal requirements.
Basic qualifications:
