Principal Design Engineer - San Jose, United States - Cadence Design Systems
Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
DSP Design Verification Engineer
Position Description
Key member of the Tensilica DSP team within Cadence, responsible for design verification of DSP based hardware products as part of families of Tensilica DSPs and hardware accelerators, targeting various application domains such as computer vision, AR/VR, audio/voice, Radar, AI or ADAS/AD.
Be part of an agile team with experts in DSP architecture, design, implementation, and HW/SW verification. Gain understanding of the DSP algorithms and mathematical functions being implemented. Architect and implement verification environments and tests to ensure that the implementation is correct, there are no functional bugs, and the performance criteria were met. Design, implement and maintain large scale regression frameworks that improve quality and project execution time.
RESPONSIBILITIES:
+ Collaborate with architecture/design team to understand the algorithms and mathematical functions.
+ Define and develop detailed test plans.
+ Develop tests in C/C++ to create a behavioral model of the DSP functions, using fixed point or floating point arithmetic.
+ Develop and maintain extensible/large scale regression flows and infrastructure, including tools for aggregating metrics and trending.
+ Develop System Verilog/UVM testbenches and checkers.
+ Apply formal verification methodology for verification sign off and quality.
+ Develop and apply novel techniques for verifying performance of designs.
Position Requirements:
+ Knowledge of DSP arithmetic functions. Domain specific knowledge in Audio, Computer Vision, AR/VR, Radar or AI desirable but not necessary.
+ Knowledge of computer architecture, especially hardware micro-architecture, processor pipelines and instruction sets.
+ Familiarity with hardware verification concepts such as assertions, scoreboard, and some knowledge of System Verilog.
+ Strong understanding of Software development.
+ Proficiency in C/C++.
+ Proficiency in any scripting language (Python or Perl preferred).
+ Familiarity with source code control (Git/Perforce).
+ Ability to work efficiently with remote teams on different time zones
+ Ability to work successfully both independently and in a team environment
+ Strong problem-solving skills, flexible, adaptable and proactive
+ Strong communication skills
+ MSEE, MSCS, or MSCE or equivalent.
+ MS and 3+ years of working in a design or verification role, or some internship experience if pursuing a PhD.
The annual salary range for California is $128,100 to $237,900. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.