- Review industry standard specs and ensure IPs are kept up to date for compliance.
- Define design partitioning for efficient IP/sub-system/full chip implementation.
- Review and provide feedback on verification plans and methodology.
- Drive block/chip/system level development and execution.
- Work with Hard IP designers, verification, validation, Firmware engineers, and architects to produce thoroughly verified, robust IP.
- Actively participate in post-silicon bring-up, validation and compliance testing.What You Need for this PositionMust have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with years of experience:
- years of experience in logic design using Verilog/System Verilog
- Very strong domain knowledge about PCIe/CXL
- Proven track record of taking several chips in from product definition to production.
- Experience in complex ASIC design.
- Good understanding of ASIC design and verification methodologies and flows.
- Architecture/Micro-architecture definition
- Design partitioning and Hard IP interactions
- Multiple async clock domain designs
- Design for test
- Clock/Reset
- Power-aware
- Excellent understanding of Synthesis, STA, CDC, Lint, LEC
- Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
- Proficient in Perl scriptingSo, if you are a Sr. ASIC Design Engineer with PCIe and/or CXL experience, please apply today or send an updated copy of your resume to for immediate considerationApplicants must be authorized to work in the U.S.Preferred SkillsASIC DesignRTL DesignMicroarchitecturePCIeCXLUARTI2CSPI FlashVerilogSystem Verilog
Sr. ASIC Design Engineer - San Jose, CA, United States - CyberCoders
Description
San Jose, CA Full-time $175, $225,000.00Posted 03/01/2024Job Title: Sr. ASIC Design Engineer - RTL, PCIe, CXLJob Location: San Jose, CACompensation: $175K - $225K+ base Depending on experience plus stock optionsRequirements: RTL Design, ASIC Design, Microarchitecture, PCIe, CXL
We were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions. AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.
We are working on a CXL/PCIe-based chip for cloud computing applications. We're expanding our team and looking to add a Sr. ASIC Design Engineer.Top Reasons to Work with Us1) Competitive Compensation ($175K - $225K+ base Depending on Experience)2) Comprehensive Benefits package including stock options
3) The chance to join a small start-up tackling challenging problems with huge upside potentialWhat You Will Be Doing- Participate in architecture definition and modeling.- Contribute to micro-architecture specification and reviews.