Design Verification Engineer - Austin, United States - Zenex Partners

Description

About Zenex Partners: Zenex Partners is a leading global human resource consulting firm dedicated to assisting companies in recruiting the right talent, managing their HR functions, and expanding globally. As a trusted recruiting partner, we offer extended HR services to streamline organizational processes and ensure compliance with HR regulations. Our diverse workforce solutions cater to organizations worldwide, simplifying their recruitment needs and facilitating rapid market entry without the complexities of legal entity setup.

Job Summary: As a Design Verification Engineer, you will play a pivotal role in the functional verification of GPU Subsystems, specifically Shader, Texture, and Memory Systems. Your expertise will contribute to ensuring the reliability and performance of these critical components in advanced GPU architectures.

Responsibilities:

• Triage regression failures and implement necessary testbench updates.
• Debug functional errors in RTL models using simulation and debug tools.
• Maintain an efficient and clean regression status.
• Develop scalable SystemVerilog/UVM testbenches for unit-level and/or cluster-level verification.
• Review Architecture and Micro-Architecture specifications.
• Collaborate closely with Architects and RTL designers.
• Define, maintain, and execute unit-level and/or cluster-level verification test plans.
• Generate and execute test cases on logic simulation models.
• Implement functional coverage models and SystemVerilog assertions.
• Drive Functional Coverage and Code coverage to closure.
• Integrate C++ reference models into Scoreboards.

Requirements:

• 5-15 years of industry experience in a design verification role.
• Proficiency in SystemVerilog/UVM/OVM, OOP/C++.
• Knowledge of GPU, with experience in Shader, Texture, or Memory Systems preferred.
• Experience with code coverage and functional coverage-driven verification methodologies.
• Experience in creating, running, and debugging SystemVerilog/UVM constraint-random Testbenches.
• Excellent working knowledge of scripting languages such as Python or Perl.
• Understanding of micro-architecture, logic design, FSMs, and arithmetic datapath pipelines.
• Strong functional verification experience, including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
• Strong debugging skills.
• Strong programming skills with a good understanding of algorithms and data structures.
• Good verbal and written communication skills.

Candidate local to the Austin market

Current state-of-the-art testbench development such as UVM methodology

Experience in design verification with UVM and SystemVerilog is a MUST