- Strategize and execute cache coherency subsystem verification efforts across verification platforms
- Review architecture and microarchitecture specs and influence design/microarchitecture decisions
- Define verification strategy and test plans for cache coherency subsystem verification
- Architect and lead development of verification collateral including test benches, random test generators and checkers
- Lead and contribute to day-to-day execution of all verification activities to meet tape out quality requirements
- Define post-si validation plans and debug post-silicon system level failures
- Mentor/guide the work of other engineers to achieve project goals
- Minimum MS & 8 years or BS & 12 years of
IP and subsystem design verification experience - Solid understanding of
high-performance multi-core processor architecture and microarchitecture,especially OOO memory and cache coherency protocols - Prior experience in verifying
Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols or other high performance interconnect protocols. - Experienced in building new verification test benches using industry standard languages like
System Verilog, UVM/OVM - Programming experience in 1 or more languages common to the industry (e.g., C, C++)
- Experience in automating design/verification tasks using perl/python or other scripting languages
- Knowledge of ARM or x86 memory architecture and assembly language programming
- Prior experience in leading design verification efforts and strong verification mindset with excellent attention to detail
- Technical leadership skills like ability to articulate vision, inspire the team, plan, and organize team's work, make difficult decisions
- Strong analytical and problem skills and able to communicate technical concepts, status, and issues clearly
- Previous experience in CPU/core design verification is preferred
- Previous experience in emulation, FPGA and post-silicon validation is preferred
- BS/MS Electrical Engineering or Computer Engineering
- Office has panoramic views of Silicon Valley
- Garage parking, including charging stations and bike parking
- Gym and caf on campus
- Healthy snacks, espresso, and drinks
- Standing desks
- Game room, including ping-pong
- Unlimited Flextime + 11 paid holidays
- Modern and open office setting
- Four miles of jogging and pedestrian trails
- Walking distance to various restaurants and shopping
- Healthy snacks, espresso, and drinks
- Adjustable sit-stand desks
- Unlimited Flextime + 11 paid holidays
- Walking distance of breweries, landscaped parks, art galleries, restaurants, and shops
- Garage parking
- On-site bike parking and repair station
- Gym
- On-site caf, bar, and market
- Roof top terrace with Willamette River views
- Healthy snacks, espresso, and drinks
- Standing/Ergo friendly desk set up
- Game room
- Unlimited Flextime + 11 paid holidays
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Ampere Santa Clara, United States· Come invent with us and change the future of computing · We are building a team of pre-silicon design verification (DV) engineers throughout our US locations to help us guarantee the first silicon success of our upcoming roadmap. · Ampere has the leadership, discipline, and ...
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Ampere Santa Clara, United States· Come invent with us and change the future of computing · We are building a team of pre-silicon design verification (DV) engineers throughout our US locations to help us guarantee the first silicon success of our upcoming roadmap. · Ampere has the leadership, discipline, and ...
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Senior Principal Engineer, Cache Coherency Subsystem Verification - Santa Clara, United States - Ampere
Description
Come invent with us and change the future of computing
We are building a team of pre-silicon design verification (DV) engineers throughout our US locations to help us guarantee the first silicon success of our upcoming roadmap.
YOU
The Role
This role is for anyone of our US locations (Santa Clara, CA., Portland, OR., Raleigh, NC, or remote US)
As a Senior Principal Cache Coherency Subsystem Verification Engineer, you will the opportunity to work on and lead the verification of a server-class microprocessor-based Coherent Mesh interconnect subsystem.
You'll be involved with all aspects of pre-silicon verification of the subsystem to ensure functional correctness and performance of our CPUs.
You'll also partner with other teams to accelerate post-silicon validation and debugging of the product.What The Team Wants You to Know
Design Verification is an integral part of the chip design process that ensures our customers get the absolute highest quality products that meets their functional and performance requirements.
The DV Team at Ampere comprises of stellar folks who have dedicated themselves to the art and fun of design verification.
We are a tightly-knit, fast-paced team who work extremely closely with our design and architecture partners to ensure no bug is left behind.
What You'll Do:
What You Must Bring to
The Table:
Education:
Perks in Santa Clara
Perks in Raleigh
Perks in Portland
Pay and Benefits
Ampere offers a competitive total rewards package that includes base pay, bonus, stock, and comprehensive benefits.
The full base pay range for this role is between $129,000 and $215,000, except in the San Francisco Bay Area where the range is between $143,000 and $238,000.
We also offer an annual bonus program tied to internal company goals and annual meritocratic stock awards that enable our employees to participate in the success of the company.
Our benefits include health, wellness, and financial programs that support employees through every stage of life, with full benefits eligibility at 20 hours per week.
Beyond compensation and benefits, our passionate teams thrive in an inclusive culture that empowers our employees to do more and grow more - all in service of inventing industry leading cloud-native designs that contribute to a more sustainable future.
We look forward to sharing more about our career opportunities through interviews but reach out to [email protected] if you have questions that can't wait.
Our Company
Ampere is designing the future of hyperscale cloud and edge computing with the world's first cloud native processor.
Built for the cloud with a modern 64-bit Arm server-based architecture, Ampere gives customers the freedom to accelerate the delivery of all cloud computing applications.
With industry-leading cloud performance, power efficiency and scalability, Ampere processors are tailored for the continued growth of cloud and edge computing.
Our Story
Like the scientist behind its name, Ampere employees are innovators. We understand the needs of cloud computing and different software requirements.
We are inventing what comes next and looking at everything from the structure of memory and how efficient the system is, to considerations on speed, cost of electricity and ability to cool.
Power, size, weight, and cost are driving the technology requirements and the innovation to come.
Our world class team of engineers, with depth and expertise in the cloud and semiconductor industries, is not only focused on the development of new semiconductor designs but also building out the first software ecosystem for Arm-based server processors.
Through the Ampere approach to the cloud and edge, we give our customers the freedom to challenge the status quo and accelerate next-generation data centers for the most memory-intensive applications.
Given the challenge we have outlined, we are building a culture of entrepreneurs that ensure customers come first, proactively approaching industry challenges in the areas of security, power, and performance, delivering results that matter most.
#LI-GW1
#LI-Hybrid
We are an inclusive and equal opportunity employer and welcome applicants from all backgrounds.
All applicants will receive consideration for employment without regard to age, race, color, religion, sex, national origin, disability status, protected veteran status, or any other characteristic protected by law.
