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- Micro-architecture specifications and participate in specification and test plan reviews.
- Architect and implement complex RTL designs.
- Integrate CPU and other relevant IPs into the CPU sub-system.
- Work with the physical design team to resolve implementation and timing issues and to optimize power.
- 8+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
- Experience in IP integration, specifically CPU IP into SoC.
- Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
- Strong UVM exp.
- Familiarity with AMBA/APB/AXI Protocol
- Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....
- B.S. (M.S. preferred) degree in Electrical or Computer engineering.
Sr.-Principal ASIC Design Engineer - San Diego, United States - Tripod Networking
Description
Location:
Learn more about the general tasks related to this opportunity below, as well as required skills.San Jose, CA or Remote
Will transfer H1's.
Will consider relocation if needed.
Responsibilities:
Required Qualifications: