Principal ASIC Design Verification Engineer - San Jose, United States - CyberCoders

Description

San Jose, CA Compensation UnspecifiedPosted 04/26/2024

Job Title:
Principal ASIC Design Verification Engineer - UVM, PCIe, CXL

Job Location:
San Jose, CACompensation: $180K - $240K base Depending on experience plus stock optionsRequirements: ASIC Design, Verification, UVM, PCIe, CXL

We were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions.

AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.

We are working on a CXL/PCIe-based chip for cloud computing applications. We're expanding our team and looking to add a Principal ASIC Design Verification Engineer.
Top Reasons to Work with Us1) Competitive Compensation ($180K - $240K base Depending on Experience)2) Comprehensive Benefits package including stock options
3) The chance to join a small start-up tackling challenging problems with huge upside potentialWhat You Will Be Doing- Test bench development using System Verilog UVM- Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections

• Regression setup and debug at RTL level and gate sim level working with the design teamWhat You Need for this PositionMust have a Bachelor's (Master's or Ph.

D.

preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10+ years of experience:

• Design Verification experience
• Deep knowledge of System Verilog, UVM, and verification coverage matrix
• Familiar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP
• Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP)
• Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
• Proficient in Perl scriptingSo, if you are a Principal ASIC Design Verification Engineer with UVM and PCIe and/or CXL experience, please apply today or send an updated copy of your resume to for immediate considerationApplicants must be authorized to work in the U.S.Preferred SkillsVerificationPCIeASIC DesignUVMCXLUARTI2CSPI FlashSynopsysMentor Graphics