RTL Design Engineer - Los Angeles, United States - Acceler8 Talent

Description

We are seeking an RTL Design Engineer to join a well-funded startup whose vision is to bring their energy-efficient programmable processor to market.

This startup has completely thrown out the existing Von-Neumann computation model and are solving problems in a different way with a much more general approach.

As opposed to a dedicated accelerator, they use a proprietary ISA conversion using their compiler that lays it out onto a general purpose array.

Responsibilities:
Responsible for the manipulation, integration, and verification of Verilog models of SRAM to meet design specifications and requirements.
Leverage extensive experience with vendor-provided Intellectual Property (IP) to collaborate effectively with external providers and integrate third-party modules seamlessly.

Develop an in-depth understanding of the memory hierarchy within the system, including but not limited to cache architectures and memory banks, to enhance system performance.

Engage in the design and optimization of memory allocation and data flow, ensuring robustness and compliance with technical and industry standards.

Collaborate with the design team to identify and resolve memory bottlenecks and to implement solutions that optimize memory usage and access patterns.

Qualifications:
PhD or MS in EE or related fields + 5-8 years' RTL Design experience.
Experience with a variety of RTL Designs (CPUs, Accelerators, Energy, Simulation, UPF, Clock Domain Processing, etc.)
Experience working with vendor provided IP.
Experience working on a project from Day 1, from concept to production.
Strong experience in SoC integration and processor design.

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