Staff STA Engineer - San Diego, CA

We are currently hiring for the position of Staff STA Engineer in San Diego. The job involves working with Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. · ...

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology. · ...

Imagine what you could do here At Apple new ideas have a way of becoming extraordinary products services and customer experiences very quickly. · B · The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave th ...

Imagine what you could do here At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. · ...

Imagine what you could do here At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. · ...

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology. · ...

Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of Signoff solutions for the Snapdragon chips powering billions of mobile devices. · ...

Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of Signoff solutions for the Snapdragon chips powering billions of mobile devices. · ...

As a Timing Engineer you will play a vital role in timing analysis targeting the Mobile Compute Automotive and IOT markets · The candidate will work with best-in-class methodologies tools and technology to design innovative SOC products at the block/IP-level and at system-level i ...

The position requires Signoff Timing and spice simulation experience. · Improving the Timing and Cell Characterization methodology for diverse Mobile chips. · Collaborate with AI team on initiatives for compute reduction. · ...

Do you have a passion for invention and self-challenge? As part of a world class modem team, you'll be at the heart of chip design. · As an ASIC STA engineer, you will be responsible for all aspects of timing including working with designers for timing constraints generation, · R ...

We have an opportunity for a results-oriented and outstandingly hardworking Timing Design Engineer. · Description · As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing.You will closely interact with RTL designer to underst ...

Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of Signoff solutions for the Snapdragon chips powering billions of mobile devices. · Improving the Timing and Cell Characterization methodology for diverse Mobile, Compute, AI, IoT Snapdragon chips. · ...

+Job summaryDo you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible. · +Perform static timing analysis across multiple corners and modes using tools like Synopsys PrimeTime. · ...

As part of a world class modem team you'll be at the heart of chip design Apple recently announced first in-house 5G modem platforms · ...

As a Timing Design Engineer at Apple, you will have responsibilities spanning all aspects of SoC design in terms of timing. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical desi ...

The Graphics team is looking for Experienced Physical Design Engineers to work on Adreno Graphics cores in the area of Physical Implementation. · ...

We are looking for a Senior Digital IC Design Engineer to lead the designing, · developing and validating a variety of digital integrated circuit blocks and systems. · ...

The QCT DDR PHY team develops high-speed/low-power DRAM memory interface for all Qualcomm chipsets in latest DDR technologies.This position requires involvement in static timing analysis (STA) and closure of DDR PHY interface and internal logic components operating on high speed ...

The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond. You will be working with physical design team (and other teams) on timing closure, CAD teams, IP team ...