Senior Physical Design Engineer - Los Angeles, United States - Cadence Design Systems

Description

Cadence

is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise.

The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

The unique "One Cadence – One Team" culture promotes collaboration within and across teams to ensure customer success
Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Posting Title:
Principal Product Engineer, Synthesis

Location:
San Jose, CA

Job Description
Seeking a highly motivated engineer who can drive improvement to Cadence's synthesis products from a design perspective.

The position provides an excellent opportunity to work closely with the R&D team to define the roadmap of the products.

The candidate should have:
(1) Prior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis
(2) Understand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes
(3) Industry Experience with Cadence EDA tools in the IC digital implementation flow, preferably on Genus/RC and Innovus/EDI.
(4) 5+ Years of experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and Top Level Designs.
(1) Requires a BS or MS in EE with experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes.
(2) Automation skills using Perl, Tcl and shell scripting essential.
(3) Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D
(4) Logic design and timing closure skills
(5) Proven track record and experience working in a fast paced environment

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