Analog Integration Design Lead - San Jose, CA
11 hours ago
Job description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
The Role
We are seeking an experienced Analog Macro Integration Lead to own macro- and project-level integration for high-performance ICs. This role combines technical leadership in analog/mixed-signal design with hands-on responsibility for IPCR/Totem/EMIR flows, database/library management, and cross-functional coordination to ensure SOC IP delivery and tapeout readiness.
The Person
You have a passion for high speed design with innovative and creative ideas to solve complex design challenges. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsibilities
- Act as the primary technical coordinator for macro-level IP integration and tapeout readiness.
- Coordinate with mid-level block owners to support macro IPCR flows and resolve integration issues.
- Manage IPCR releases and run Totem/EMIR for macro verification.
- Maintain and manage integration databases and library assets required for macros.
- Work closely with AMD CAD and FTO teams to debug and resolve macro-level flow issues.
- Support project-level onboarding and provide SOC IP delivery / tapeout QA.
- Troubleshoot integration problems across layout, CAD, verification, and packaging teams.
- Mentor and guide engineers involved in macro-level integration tasks.
- Strong IC design experience, with significant experience in analog/mixed-signal design and macro-level integration.
- Hands-on experience with Totem and EMIR runs.
- Analog design experience in sub-micron technologies.
- Strong familiarity with Cadence Virtuoso and the Cadence tool suite.
- Proficiency in Unix/Linux environments and scripting (Perl, Python, TCL, or similar).
- Strong organizational skills and the ability to manage multiple concurrent deliverables.
- Excellent interpersonal and communication skills for cross-functional coordination.
Preferred Experience
- ESD design/verification experience.
- Experience debugging CAD flows and interpreting tool log files.
- Experience with database/library management for tapeout flows.
- Prior experience coordinating SOC IP delivery and tapeout QA.
Academic Credentials
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
LOCATION:
San Jose, CA
Benefits offered are described:
AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
Similar jobs
We are looking for a Lead Designer with a passion for design and a talent for making delightful experiences · Create high quality, forward thinking, visually engaging designs. · Create easy-to-use & frictionless UX. · ...
1 week ago
This position can be based out of our San Jose CA office or fully remote. · About ArchKey · We're electrifying the nation energizing the future and bringing communities to life like never before What we do today shapes vision of tomorrow Our work impacts lives long after building ...
3 weeks ago
Lead the design development of one of the BSVII transit stations. · Lead the design development of one of the BSVII transit stations. · Coordinate with other teams in developing the detailed design of the stations. · ...
1 week ago
There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. · ...
1 week ago
Project Design Lead, Nexperia USA Inc., San Jose, CA: · Design digital logic circuits for integration into mixed-signal integrated circuits (ICs), including finite state machines, control logic, data path components, and interface blocks, based on product requirements and system ...
18 hours ago
We are seeking a motivated and detail-oriented Design Lead for our Airframe team. · ...
1 month ago
+8 years experience working as a user experience practitioner within a dynamic UX group. Proven ability to deliver innovative experiences for Mobile, Tablet and Desktop form factors. · Experience defining and delivering multi-faceted service driven experiences across one or many ...
1 week ago
This position can be based out of our San Jose, CA office or fully remote. As the Engineering Design Lead – Fire Alarm, you will develop and prepare detailed fire alarm engineering drawings and construction documents for the purposes of supporting our field technicians with chall ...
1 week ago
A successful candidate will join a team designing and developing Lattice Foundation IP at Penang to help strengthen broad technical ownership of IP deliverables. · ...
3 weeks ago
Lattice is a worldwide community of engineers, designers and manufacturing operations specialists in partnership with world-class sales, marketing and support teams. · ...
1 week ago
Lattice is a worldwide community of engineers, designers and manufacturing operations specialists in partnership with world-class sales, marketing and support teams. · 20yrs experience of hardware IP and integration designLed a team of cross-functional engineers across multiple s ...
1 week ago
Lattice is a worldwide community of engineers who are developing programmable logic solutions. · ...
1 week ago
Altera is seeking a Design/DFT Physical Design Integration Lead to join our SoC Physical Design Team. · ...
1 week ago
· We are seeking a Design/DFT Physical Design Integration Lead to join our SoC Physical Design Team. · We offer a dynamic work environment, cutting-edge technology, · and opportunities to grow your career while shaping the future of compute. · A competitive salary and benefits p ...
1 month ago
Lead Design Verification Engineer - SoC/ASIC. Must have led/be leading teams. · ...
2 weeks ago
A global leader in the fabless semiconductor space powers billions of devices annually—ranging from mobile phones and smart home systems to automotive platforms and edge AI. · ...
1 month ago
Astera Labs is hiring a Lead IC Package Designer with extensive experience in complex ASIC package design using Cadence APD. · ...
1 month ago
Astera Labs es una empresa que desarrolla soluciones de conectividad personalizadas para remover obstáculos en cargas computacionales intensivas como inteligencia artificial y aprendizaje automático. · ...
1 month ago
We are developing the world's most energy-efficient general-purpose computer processor. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. · Lead physical design team from synthesis to sign-off and tap ...
1 month ago
As the ASIC Design Lead you will be responsible for leading the architecture design and implementation of our AI inference chips. · ...
2 weeks ago
+We are seeking an experienced Lead UX/UI Designer to spearhead the user experience and interface design for our web application portfolio.+ · +This role combines strategic design thinking with hands-on execution, requiring both individual contribution and team leadership capabil ...
1 month ago