Senior Design Technology Co-Optimization Engineer - Sunnyvale

Only for registered members Sunnyvale, United States

2 weeks ago

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Full time $156,000 - $229,000 (USD)

Job summary

Drive cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU.

In this role, you will bridge the gap between process technology and product architecture to define the next generation of datacenter-class silicon. You will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.
  • Execute high-fidelity Place and Route (P&R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on datacenter-class IP.
  • Drive Design Technology Co-Optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery).

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