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- As a Formal Verification Engineer, you will be responsible for adding relevant constraints, assertions, and coverage points to new and existing blocks, verifying various sequential equivalence scenarios such as clock gating, and verifying datapath equivalence of C and RTL models.
- You will diagnose formal failures and work closely with RTL designers to update formal constraints or RTL code in order to fix the failures.
- BSEE, Computer Engineering, or Computer Science and 3+ years of experience
- Masters or Ph.D degree preferred
- Good understanding of CPU and/or GPU design architecture
- Basic RTL and SystemVerilog skills can read and understand designs, testbenches, and SVA
- Experience with formal tools such as VC Formal, Jasper Gold, or Questa Formal
- Excellent communication skills and be able to work with cross-functional teams to execute verification plan
- Proficiency in scripting languages such as Python, Perl, or Tcl
- Strong capability to read high-level design specifications and RTL to create and execute formal verification plans.
Design Verification Engineer - San Jose, United States - Zenex Partners
Description
Formal Verification Engineer
6 months contract with possibility of extension
San Jose, CA (Hybrid)
Description
Skills and Qualifications