Formal DV Lead Engineer - Sunnyvale
Only for registered members Sunnyvale, United States
5 days ago
* This salary range is an estimation made by beBee
Job summary
As a formal verification engineer, you will be responsible for developing a formal micro-architecture specification, proving properties of the design, and working closely with design teams to help improve the micro-architecture.
Responsibilities
- Working with Silicon's world-class design engineers to develop a formal micro-architecture specification
- Developing comprehensive formal verification test plan that includes unique verification requirement
- Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture
- Crafting novel and creative solutions for modelling and proving robustness of complex design micro-architectures
- Developing and implementing re-usable and optimized formal models and verification code base
- Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity
Job description
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