Principal IP Design Engineer - Mountain View, CA

Overview · Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technol ...

Job description

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a
Principal IP Design Engineer
to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

Security is a fundamental pilar of Microsoft's promise to customers enabling trust in our products. To achieve this goal, the Security IP Solutions (SIS) team in Shared and Customized IP & Silicon (SCIPS) organization owns custom silicon security for Microsoft. The team develops custom cryptographic accelerators and bespoke security subsystems.

We are looking for a
Principal IP Design Engineer
to join the Security IP Solutions team.

Responsibilities
Position responsibilities will include:

• Contribute to Security IP Roadmap Design: translate system/security architecture goals into project plans, milestones, and deliverables across multiple IP blocks/subsystems.
• Hands-on Design Lead: Design leads for large subsystems or complex IP cores.
• Drive end-to-end delivery of Security IP RTL and integration: oversee micro-architecture → RTL implementation → FE customer integration program needs (schedule + quality)
• Enforce design quality and signoff rigor: define/optimize processes, best practices, and quality checks (e.g., lint/CDC/RDC-style hygiene, release criteria) to achieve "first-time-right" outcomes.
• Embed "security as a product feature" into engineering execution: drive threat-informed design decisions, security posture accountability, and crisp communication of risks/priorities to stakeholders and leadership.
• Predictable Execution: Track execution using ADO Tasks and ensure we are on track vs the plan.
• Customer Obsessed: Partner with customers to ensure clean collaboration and feedback informing design execution, ensuring highest possible customer satisfaction.

Qualifications
Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications

• Bachelor of Science in Electrical or Computer Engineering
• 15+ years of experience in hardware design.
• 10+ years of experience in Synthesis, Timing constraints, Power Performance Area (PPA) trade-offs.
• 10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in System Verilog and Clock Domain Crossing (CDC)/ Reset Domain Crossing (RDC) and LINT closure.
• Worked with leading-edge technologies 5 nm and newer.
• Experience as author of a UPF for low power design.
• Experience in developing high-speed designs.
• Ability to understand scripting tools and implement scripts in Python using AI assistance.
• Knowledge of cryptography algorithms like AES, SHA, ECC, RSA.
• Experience with industry standard certification like NIST.
• Experience with chip design quality through checklist reviews.
• Self-motivated with effective communication and influencing skills.
• VS Code and use of AI LLMs.

SCHIE #CSME

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about
requesting accommodations.