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Moreno Valley

    Senior Staff Engineer, AI Accelerator - California, MO, United States - Conductor

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    Description

    What You'll Do

    TheAdvanced Controller Development(ACD) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash. ACD's vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. We are an integral part of Samsung's strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

    Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You'll focus on enhancement of memory and storage capability by developing the prototype controller and optimize it for mass production.

    Location: Hybrid, working onsite at our San Jose, CA location 3 days a week, with the flexibility to work remotely the remainder of your time.

    Job ID: 41652

    • Drive architectural definition of AI/ML accelerator for LLM applications.
    • Lead PPA tradeoff analysis to achieve requirements.
    • Work closely with software and firmware architects to come up with optimized architectural solutions.
    • Participate in the definition of SoC architecture.
    • Participate in the development of AI/ML accelerator.
    • Work closely with design verification team for debug, to meet code and functional coverage targets.
    • Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.

    What You'll Bring

    • BS in Computer/Electrical Engineering or Computer Science with 15+ years of working experiences in silicon development or MSin Computer/Electrical Engineering or Computer Science with 13+ years of relevant working experience or PhD and 10+ years of relevant working experience preferred.
    • Experience in AI/ML accelerator architecture and design.
    • Good knowledge in CNN, Transformer Network.
    • Well versed in RISC-V architecture.
    • Experience in micro architecture of SoC, interface sub systems, logic modules.
    • Good knowledge in ASIC design flow.
    • Experience in complex logic designs and timing closure on the large sophisticated designs.
    • Self-motivated problem-solver with an ability to work well in a team.
    • You're inclusive, adapting your style to the situation and diverse global norms of our people.
    • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
    • You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
    • Innovative and creative, you proactively explore new ideas and adapt quickly to change

    #LI-SF1

    #J-18808-Ljbffr


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