Senior RTL Design Engineer - Santa Rosa - Oho Group Ltd

    Oho Group Ltd
    Oho Group Ltd Santa Rosa

    15 hours ago

    Description

    Stealth Mode Start-Up - ASIC Design, RTL, Architect

    We are seeking a Senior Design Engineer to lead architecture, design, integration, and implementation of advanced SoCs, with focus on high-speed interconnects, IP integration, and ASIC execution. Role emphasizes SoC integration with UCIe die-to-die interfaces, HBM subsystems, and custom compute cores.

    Responsibilities include RTL design, IP configuration and integration, synthesis, and collaboration with physical design teams for timing closure.

    Supports next-generation compute architectures, ensuring efficient interaction between UCIe, NoC interconnects, memory systems, and custom processing elements. Involves architecture definition and implementation of complex SoC and base die products.

    Key Responsibilities

    • Define SoC and subsystem architecture (UCIe, NoC, memory controllers, PHYs, compute cores)
    • Integrate high-speed IP (UCIe or similar) and configure NoC interconnects
    • Develop micro-architecture, RTL, and perform RTL quality checks
    • Run synthesis, lint, CDC/RDC, timing, power closure, and support silicon bring-up
    • Optimize RTL for power, performance, and area; drive SoC performance simulations
    • Collaborate with physical design on floorplanning, CTS, routing, and power integrity

    Required Qualifications

    • BS/MS in Electrical or Computer Engineering (or related)
    • 10+ years ASIC/SoC design, integration, and implementation experience

    Technical Expertise

    • SoC & RTL Integration: Verilog/SystemVerilog RTL design; top-level SoC integration of UCIe/HBM, memory controllers, and NoC interconnects; high-speed interface integration
      • ASIC Implementation: Logic synthesis, STA, low-power design; EDA tool experience; physical design constraints, floorplanning, timing closure; formal verification (LEC)

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