Senior Physical Design Engineer, AI Methodologies and Acceleration - Sunnyvale
16 hours ago
Job description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in physical sesign (RTL-to-Graphic Data System II) and with closing blocks on advanced technology nodes.
- Experience with both Place and Route (P&R) and Signoff tools.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience piloting and deploying new methodologies (machine Learning based or otherwise) to improve engineering efficiency or block-count throughput.
- Experience providing feedback to tool developers and familiarity with the concepts of ML driven EDA (e.g., prediction models for congestion, IR drop, timing, etc.).
- Ability to identify and articulate which parts of the physical design flow are repetitive or pattern-based versus those requiring specific architectural intuition.
- Ability to translate clean versus dirty design data to software and research teams.
About the job:
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will focus on product execution: owning partitions, driving partition convergence, and converging physical signoff domains of SoCs. However, you will leverage your physical design (PD) domain expertise to serve as a critical partner with the world-renowned Google DeepMind (GDM) research group. You will not simply be a user of tools, but a partner in defining them and maintaining a foot in active product cycles, you will identify the specific place and route (P&R) and signoff bottlenecks that limit engineering bandwidth. You will work with GDM researchers to translate these "day-in-the-life" issues into solvable problem statements, and to validate their AI solutions against the rigorous demands of real-world silicon schedules.The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities:
- Own physical design blocks or partitions from RTL to-GDSII flow, executing all aspects including floorplanning, placement, clock tree synthesis, routing, and physical verification to ensure successful tape-out.
- Drive the closure of timing, power, and signal integrity for high-performance designs, utilizing your experience to navigate Engineering Change Orders (ECOs) and design rule constraints.
- Collaborate with Google DeepMind to incorporate AI-driven tools into the production flow by testing new algorithms on your blocks, ensuring they provide tangible improvements in power, performance, area (PPA) and turn-around-time (TAT).
- Analyze the physical design life-cycle to distinguish between problems that require traditional engineering heuristics and those that are suitable for AI acceleration.
- Partner with Computer Aided Design (CAD) and methodology teams to transition validated AI prototypes into stable, production-supported features for the wider PD organization.
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