Principal IC Static Timing Analysis AE - San Jose, CA

Job Details: · Job Description: · We are seeking an experienced Senior Static Timing Analysis (STA) Developer to architect, design, and optimize next‑generation timing analysis engines for advanced ASIC and FPGA design flows. This role is ideal for someone who has deep expertise ...

We are seeking a highly experienced STA Engineer to support full-chip timing closure for complex high performance SoCs. · ...

Job Details · Job Description: · About The Role · We are seeking a skilled · STA DA Engineer · to support static timing analysis (STA) flows and tools across advanced digital design projects. The ideal candidate will have hands-on experience with Synopsys PrimeTime and Cadence Te ...

Perform static timing analysis using Tempus Signoff tool for various aspects of timing analysis flows, ECO flows and CAD tools and methodologies. · Work on SDC constraints and advanced OCV/SOCV concepts. · Deliver technical trainings and seminars within Cadence sites. · ...

The Design Center Engineering Physical Design team at Marvell in Santa Clara is seeking a Senior Staff Engineer, Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wire ...

The Design Center Engineering Physical Design team at Marvell in Santa Clara is seeking a Senior Staff Engineer for Static Timing Analysis (STA) to contribute to innovative projects using the latest technology nodes.We leverage cutting-edge EDA tools to solve complex challenges a ...

We're looking for a CAD engineer to join our Silicon Technologies group. You'll help design and manufacture our next-generation processor working on leading edge semiconductor technology nodes. · You'll ensure Apple products can seamlessly handle tasks that make them beloved by m ...

Do you love tackling highly complex challenges with a keen eye towards revealing what has been hidden to others? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC) wo ...

We are seeking a Senior Staff Engineer, Static Timing Analysis (STA) to contribute to a wide range of innovative projects. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust de ...

Minimum qualifications: · Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. · 5 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and veri ...

Minimum qualifications: · Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. · 5 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and veri ...

We are seeking a detail-oriented Cell Biology Research Associate to support the development of advanced AI-driven image analysis software. · ...

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. · ...

Minimum qualifications: · Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. · 5 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and veri ...

+We are looking for a Static Timing Analysis Manager to lead and manage our functional STA team responsible for delivering system-on-chip (SoC) Static Timing Analysis. You will be responsible for executing full chip timing signoff checklist, performing full chip STA, power recove ...

· Minimum qualifications: · Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. · 10 years of experience with silicon implementation and chip integration. · Experience with STA sign-off cons ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. · Job Duties: · Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) ...

Perform full-chip Static Timing Analysis (STA). · Develop, validate, and own SDC constraints based on architectural and micro-architecture specifications. · Define and manage primary/generated clocks, IO delays, case analysis, false paths, multicycle paths, and other timing excep ...

Job Description: · ◦ Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. · ◦ Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and powe ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. · Job Duties: · Utilizing engineering background, provide pre-sales and/or post-sales technical customer support including implementation, training, and maintenance suppo ...