- DRC/LVS runset development in ICV-PXL or Calibre-SVRF or Pegasus language.
- EDA extraction tools
- StarRC/Quantus/Calibre-xACT/xRC
- Perl, or Python or TCL. 1+ year of experience with CAD/CAE environments that involve circuit simulation, parasitic extraction, and netlisting tools.
- PDK development.
- Experience in large scale software development, debugging, and support.
- Software development practices such as Agile and Test-Driven Development.
- Physical design, layout, and verification flows.
- IC manufacturing process flows. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art
- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, c To view full details and how to apply, please login or create a Job Seeker account
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PDK Extraction Runset Development Engineer - Boise, United States - Idaho State Job Bank
Description
PDK Extraction Runset Development Engineer at Intel in Boise, Idaho, United States Job Description Job Description Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing.
Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools.
In this role you will be responsible for developing extraction runsets for one or more of the major EDA vendors on Intel's leading edge process nodes.
This includes Synopsys ICV, Siemens Calibre, and Cadence Pegasus. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution. #DesignEnablement Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:
Candidate must possess a BS degree with 4+ years of experience or MS with 3+ years of experience or PhD degree with 1+ years of experience in EE/ECE or related field.
3+ years of experience in the following:
Preferred Qualifications:
3+ years of experience in the following:
1+ year experience in the following:
