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    • NoC Systems Architect - San Jose - PER International

    PER International
    PER International San Jose

    3 weeks ago

    Default job background
    Description

    Job Title: NoC Interconnect Design Engineer

    About Our Client:

    Our client is one of the world's largest global Top-tier Semiconductor Companies, shaping the future of technology and driving innovation in the semiconductor industry.

    About the Role:

    The ideal candidate will join our NoC Interconnect design team, collaborating with architecture, modeling, silicon, software, and other design teams to create a competitive design. We are looking for hands-on individuals who are dedicated to system performance improvement.

    Key Responsibilities:

    • Design experience and knowledge in computer architecture, microarchitecture, and performance analysis.
    • Hands-on experience in RTL design, power optimization, and interconnect fail-operational architecture for function safety.
    • Familiarity with recent ARM processor micro-architectures and AMBA AXI, CHI, and LPDDR4/5 interfaces/protocols is a plus.
    • Drive NoC Interconnect and Memory System architecture and designs to optimize power, performance, and implementation.
    • Show system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.).
    • Develop and implement NoC Interconnect, validate functionality, improve design revisions, and meet performance targets as well as system requirements.

    Requirements:

    • Experience in computer architecture, microarchitecture, and performance analysis.
    • Design experience and knowledge in architecture, RTL design, performance analysis, and power optimization.
    • Familiarity with the architecture and micro-architectures of recent ARM processor is a plus.
    • Familiarity with AMBA AXI, CHI, and LPDDR4/5 interfaces/protocols is a plus.
    • Strong system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.).

    Location: San Diego, California

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