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    Sr Design Verification Engineering Manager - Columbia, United States - Cadence Design Systems

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    Description


    At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.


    Job Description:

    Roles & Responsibilities:


    The role requires the management of a SerDes DV group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.


    The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions.

    The role will require customer interactions including pre and post-sales activities: DV methodology review, customer support.

    Participate in Technical alignment with verification experts in defining verification strategy, architecting verification environment.

    Represent DV and technically work/lead team interactions with RTL, analog/modeling, PD teams for design verification tasks.

    Contribute towards defining, developing and deploying new functional verification methodologies.


    Skillsets:
    The engineers should have strong background in functional verification fundamentals, verification environment planning & development, test plan creation.


    Prior digital verification experience in some of the serial bus multiprotocol PHY IP's ( SerDes IP especially PCIe and other protocols) is expected.


    Other verification domain skills:

    • Strong expertise in Verilog, HVL( SV, e) with UVM/OVM/eRM methodology
    • Experience in assertions development/closure, constraint randomization, functional coverage, code coverage
    • Strong RTL and GLS sim debug skills
    Expertise in more than two of following skills is desirable and added plus:

    • Power aware RTL set up, simulation and debug
    • Formal verification
    • Gate level timing/no timing simulations
    • Good to have (not must have): Some experience or understanding of Analog modelling.
    Mixed-mode simulations with Analog/digital ( AMS)

    • Some exposure to Automotive IP verification (fault injection), emulation exposure though not mandatory but good to have
    We're doing work that matters. Help us solve what others can't.

    Additional Jobs )

    Cadence plays a critical role in creating the technologies that modern life depends on.

    We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.


    Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

    Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

    Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer.

    All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

    Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer.

    All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.


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