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Design Verification Engineer
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Design Verification Engineer
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Design Verification Engineer
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Design Verification Engineer
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Design Verification Engineer
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Zenex Partners Austin, United StatesDescription · Design Verification Engineer · 12 Months contract with possibility of extension · Austin, TX (Hybrid 3 - 4 days in office) · As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Sy ...
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ASIC Verification Engineer
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ASIC Verification Engineer
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NVIDIA Austin, United StatesASIC Verification Engineer - GPU page is loaded · ASIC Verification Engineer - GPU · Apply · locations · US, CA, Santa Clara · US, TX, Austin · US, NC, Durham · time type · Full time · posted on · Posted 30+ Days Ago · job requisition id · JR · NVIDIA is seeking elit ...
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System Verification Engineer
2 weeks ago
NVIDIA Austin, United StatesNVIDIA's invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU-accelerated servers acting as ...
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Design Verification Engineer
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5V Tech | Certified B Corp Austin, United StatesStaff-level SoC Design Verification Engineer · Austin, TX, USA · Up To $230,000 Per Year + 15% Bonus, RSUs, Other Benefits · Permanent, Full-time · Hybrid Working Flexibility - Remote Potential · Passionate about building the future of the connected world? Join the Mission-C ...
Design Verification Engineer - Austin, United States - Whoznxt
Description
Design Verification Engineer (GPU)6 Months Contract
Local to market in Austin, TX - - Hybrid onsite 3 days per week (No Remote candidate)
As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU.
Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.
RequirementsRole and Responsibilities:
Key Responsibilities Include
Work with architects and designers to build verification environments and test plans
Craft functional verification coverage strategy to ensure complete test suite implementation
Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
Analyze failing tests to root cause along, working with RTL and reference modeling teams
Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
Examine code coverage results, identifying exclusions and improving stimulus
Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics
Skills And Qualifications
Minimum requirements:
BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
Proficient in System Verilog/UVM/OVM, and OOP/C++
Deep understanding of constrained randomization and the development of efficient test suites
Experience with code coverage and functional coverage-driven verification methodology.
Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.
Working knowledge of scripting languages such as Python or Perl
Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines
Preferred Qualifications
MS CE/EE with 5+ years of industry experience in verification
Good verbal and written communication skills
Experience of GPU or CPU is a plus
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