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    • Design Verification Engineer - San Jose - Quest Global

    Quest Global
    Quest Global San Jose

    3 weeks ago

    Default job background
    Description

    Job Title: Senior Design Verification Engineer

    The role focuses on planning, building, and executing the verification of new and existing features for custom silicon/ASIC designs. This results in a zero-bug final design, ensuring first-time silicon success.

    About You:

    You have a passion for modern, complex processor architecture, digital design, and verification in general. As a team leader with excellent communication skills, you've collaborated with other engineers across different sites/time zones. Your analytical and problem-solving skills are strong, and you're willing to learn and take on problems.

    Key Responsibilities:

    • Collaborate with Architecture, Design, Functional DV, Emulation, Platform Debug teams to understand Architecture and verification asks.
    • Create detailed test plans based on Architecture specifications.
    • Develop a good understanding and exposure to SoC designs and architectures.
    • 12+ years of Design Verification experience with strong Verilog, System Verilog, C, and UVM/OVM knowledge.
    • Candidates should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions.
    • Own the DV sign-off and ensure a bug-free design.
    • Work with the post-silicon team on debug support and help root-cause any failures.
    • Have worked on wireless protocol design verification.
    • Bring up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow.
    • Exposure to DEBUG concepts such as JTAG etc.
    • Comfortable with VCS/Verdi and excellent debug skills.
    • Good communication and leadership skills.
    • Continuously drive methodology improvements to improve efficiency.
    • Mentor junior engineers to build a high-performing team.

    PREFERRED EXPERIENCE:

    • Proficient in SoC/sub-system/IP level ASIC verification.
    • Proficient in debugging firmware and RTL code using simulation tools.
    • Experienced with Verilog, System Verilog, C, and C++.
    • Worked on any High-Speed Interface like CXL/PCIE/DDR/USB/Other, good understanding of AXI/AHB/APB Bus protocol.
    • Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification.
    • Developing UVM based verification frameworks and testbenches, processes and flows.
    • Good understanding and hands-on experience in the UVM concepts and System Verilog language.
    • Scripting language experience: Perl, Python, Make file, shell preferred.

    Seniority Level: Mid-Senior level

    Employment Type: Full-time

    Job Function: Design and Engineering

    Industries: Engineering Services and Semiconductor Manufacturing

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