US_West | Platform Engineer - DevOps Specialist _L3 - Austin, United States - Expedite Technology Solutions LLC

Description

Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO OPT OR CPT ALLOWED.

Submit candidates under their legal name and use only *** template
Candidate s photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.


In your submission include:

Phone #:

Email address:

Location (City and State):

Relocate:

Availability to start:

Visa type and expiration date:

Hiring Status:
C2C/W2/1099


Open for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.

Candidates must be willing to go to the closest
, Client, or offsite location as indicated by project team to meet with a team member prior to starting their assignment.

If the candidate is not local, travel will be required at the expense of the *** project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement).

If travel is involved, will send travel policy document for the candidate to adhere to

Marie Samayoa
OBO Tactical Procurement | Procurement
*

• North America | Guatemala

Email:
*

• Job Description: Design Verification Engineer

Location:
AUSTIN (US:73301), TX

Onsite role

o Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)
o Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases.
o Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan.
o Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness.
o Debugging failing testcases to determine source of failure (tool, testcase, checker, Verilog RTL) and track resolution

o Collecting code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage.

Verilog, System Verilog, UVM


Job Qualifications:
o Verilog, System Verilog, UVM coding skills required.
o Verification skills (test planning, testcase, testbench, simulation, debug) required.
o Knowledge of ARM AMBA

protocols a plus.
o Knowledge of LPDDR4/5 protocol a definite plus
o Ability to work independently and in small teams without close supervision required.
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