- 5+ years' experience completing layouts of high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools.
- Creating die and BGA symbols from scratch or from spreadsheet inputs
- Setting up design environment, including tech files, stack ups, and constraints
- Setting up Constraint Manager from scratch for complex packages (diff pair creaton, multiple power supplies, net and zone-specific constraints.
- Routing signals and matching length both manually and using tool features
- Design file management and documentation from initiation to final signoff
- Generation of POD
- Solid knowledge of top package suppliers design rules and basic manufacturing practices
- Experience with Cadence Orbit I/O
- 2.5D interposer design layout experience using Cadence SiP
- Experience with Virtuoso and/or Innovus for 2.5D interposer design
- Experience with Synopsys tools for 2.5D interposer design
- Experience writing and implementing custom scripts in Cadence tools
- Familiar with Cadence PVS
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Amazon Services LLC Sunnyvale, United States Full timeAmazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronic devices. Lab126 began in 2004 as a subsidiary of Since then, we have worked to produce hardware and software for Fire tablets, Kindle Oasis, Amazon Fire TV, ...
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Chip Packaging Engineer - Mountain View, United States - Saxon Global
Description
HiHope you are doing good.
We are looking for Chip Packaging Engineer. This is a full time as well as contract position. Please check the job description and reply to me if you are available for this position.
Title:
Chip Packaging Engineer
Location:
Mountain View, CA (Day 1 Onsite)
Duration:
Full Time/ Contract
Candidate Roles and Responsibilities
Manish Kumar
P:
Email:
Linkedin:
Suite # Greenway Drive, Irving, TX 75038
Website:
#J-18808-Ljbffr