Senior Software Engineer – Logic Synthesis - San Jose, CA

· WHAT YOU DO AT AMD CHANGES EVERYTHING  · At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real p ...

We are seeking a highly motivated MS student currently enrolled in a U.S. university for a 3 month internship with our Product Engineering team. · This role offers a unique opportunity to work closely with the R&D team on Cadence's industry-leading Genus Synthesis Solution, · con ...

Hands-on experience in software development for EDA tools working closely with R&D teams. · Design implement troubleshoot and debug software programs on Unix/Linux platforms. · Develop enhance algorithms for logic synthesis and physical design flows. · ...

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology Join the Digital & Signoff Group DSG at Cadence contribute to the development of the Genus Synthesis Solution a state-of-the-art logic synthesis tool that optimizes Power P ...

Cadence is looking for an intern to develop algorithms in the physical design space. · ...

Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence's Genus Synthesis Solution product. · We're doing work that matters. Help us solve what others can't. · ...

Broadcom is looking for a senior level RTL synthesis engineer. · MS in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design · Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Ne ...

Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence's Genus Synthesis Solution product. · Proficient in C/C++ · Excellent programming and software engineering skills · Experience with UNIX and/or LINUX platfor ...

Lattice Overview · There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and m ...

The RTL Synthesis Engineer will debug timing/area/congestion issues and work with RTL & Physical designers to resolve them. · ...

We are looking for an experienced Physical Design Engineer to join our Silicon Engineering team.The ideal candidate has strong hands-on experience in block-level physical implementation and timing closure. · Bachelor's or Master's degree in Electrical Engineering, Computer Engine ...

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for C-HBM component IPs including TSV interconnects. Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for HBM component IPs (PHY, controller, interconnects, tr ...

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for C-HBM component IPs including TSV interconnects. · We are seeking an experienced RTL designer with a strong background in digital design and verification. The ideal candidate will ha ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. · Job Duties: · Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) ...

About the Role · As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-o ...

This position is responsible for debugging timing/area/congestion issues and working with RTL & Physical designers to resolve them. · Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. · Run Formal Verification checks between RTL and G ...

The DSP Design Engineer will oversee definition, design, verification, and documentation of state-of-the-art, AI-enhanced DSP IP for next generation FPGA families. · Design and implement high-performance DSP IP for next-generation FPGAs · Contribute to all phases of the design li ...

The DSP Design Engineer will oversee definition, · design, verification and documentation of state-of-the-art AI-enhanced · DSP IP for next generation FPGA families. · Design and implement high-performance DSP IP for next-generation FPGAsContribute to all phases of the design lif ...

Broadcom is looking for a digital signal processing engineer to design digital signal processing blocks for the next generation of optical data center connectivity products. · ...

DFT Lead/Architect with 15+ years of experience in DFT engineering and architecture. · Creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes · Familiar with DFT verification, silicon debug, memory and scan diagnostics. · ...