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CPU Verification Engineer - Austin, United States - Taleo BE
Description
Job Details:
Job Description:
Performs functional verification of CPU logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests.Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of architecture and microarchitecture features of the CPU being designed actively.Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Requirements:
Master's in computer engineering or electrical engineering or STEM related degree plus 2 years of relevant work experience OR a bachelor's in computer engineering or electrical engineering or STEM related degree plus 3 years of relevant work experience.
Computer architecture knowledge, including specific areas of technical ownership/expertise relevant to CPUs
Validation environment development in C++, Verilog, System Verilog UVM/OVM
Strong programming experience in at least one language: C/C++, Perl, Python, etc.
Preferred Requirements:
Knowledge of Intel Architecture ISA and system architecture, x86 assembly language.
Familiarity with software validation, including microcode, firmware, etc.
Experience in post-silicon debug and analysis
Intel or industry experience in micro-architecture, design or verification of CPU cores
Experience with a hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools
Validation and debug experience including test writing/generation, checker development, coverage analysis, failure debug, root cause analysis
Assembly language programming, code generation, or other low-level software experience.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products.
From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations.
DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams.
As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/AWork Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.#J-18808-Ljbffr
