- Define, participate, and develop critical compiler modules including front-end graph optimizations, additional hardware-aware optimizations, back-end code generators and low-level library (kernel) development.
- Use performance-driven methodologies to define a comprehensive set of compiler optimizations needed to enable high-performance AI inference solutions.
- Collaborate closely with the AI architecture, algorithms and runtime teams to create and optimize end-to-end performant AI solutions.
- Interface with teams building chip-simulators, performance models, assemblers, and disassemblers for EnCharge AI architectures.
- Create SDKs to interface custom compiler stack with popular AI frameworks & runtimes.
- Work closely with the AI Architecture and FPGA platform teams to jointly optimize the compiler stack and architecture - with the goal of enhancing system level performance for AI applications.
- Masters/Ph.D. in EE/CS with >5 years of industry experience in compiler development and / or chip architectures (preferably AI chip architectures).
- Proficiency with C++, Python and Systems programming.
- >5 years of experience in compiler and / or library design (in R&D and / or products).
- Knowledge of industry-standard (and advanced) tools, graph, and intermediate-representation (IR) formats and methodologies including LLVM, MLIR and TVM.
- Familiarity with Tensorflow & PyTorch AI frameworks.
- Solid understanding of AI Applications and performance bottlenecks.
- Excellent verbal and written communication skills.
- Experience with CI/CD.
- Knowledge of the end-to-end runtime stack for AI applications.
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Artificial Intelligence Compiler Engineer - Santa Clara, United States - EnCharge AI
Description
Role/Responsibilities:EnCharge AI is looking to hire multiple software engineers (at junior and senior levels) who can help build out compiler stacks for the next generation of Edge Artificial Intelligence (AI) chips. You will have excellent software development skills as well as experience architecting and building compiler stacks for high-performance chips.