- Interfacing with customers regarding library development methodologies, including:timing characterization,EMIR view generationPhysical view generation (LEF, GDS, abstracts, etc)Logical view generation (LIB, CDL, Spectre, etc)Technology LEF creation for digital tools
- scoping the level of effort, performing library characterization, generating logical and physical views such as PGV, Verilog, LEF, DSPF, etc and supporting validation of the results
- Supporting adoption and proliferation at existing customers (on/offsite), to help drive business for our library development tools
- Working closely with R&D on tools and methodology improvements
- Create and contribute technical content for Cadence Online Support
- Other digital P&R tasks as needed by the group
- Bachelor's degree with at least 3-7 years of design/EDA experience or Master's degree with at least 4 years of experience. Master's degree preferred.
- Knowledge of standard cell and IO characterization methodology
- Excellent analog simulation and debug skills
- Experience with reliability simulation and aging effects
- Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM
- Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis
- Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred.
- Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
- Strong customer-facing communication and problem solving skills
- Strong personal drive for continuous learning and expanding professional skill sets
- Excellent verbal and written communication skills
- Characterization : Liberate, Liberate MX, Liberate AMS
- Simulators: Spectre, AMS, Xcelium
- Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc
Library Development Methodology AE - Austin, United States - Cadence Design Systems, Inc.
Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The position involves:
Position Requirements:
Familiar with EDA tool operation, setup and debug:
The annual salary range for California (Other than San Jose) is $108,500 to $201,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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