Circuit Design Engineer - Santa Clara, United States - LanceSoft

Description

Location: Folsom or Santa Clara or San Diego, CA.

Hybrid. 2-3 days onsite.

PLL Circuit Design Engineer

Key Responsibilities:

Help design of building blocks of a PLL

Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.

Work closely with layout engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

Required:

Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.

Solid knowledge of industry standard tools and practices for analog circuit design

PREFERRED EXPERIENCE:

3-5 years of professional experience in the semiconductor industry

Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm/5nm

Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.

Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.

Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.

ACADEMIC CREDENTIALS:

Masters in electrical engineering or equivalent preferred