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    Mixed Signal Verification Engineer - Hillsboro, United States - Everest Consultants

    Everest Consultants
    Everest Consultants Hillsboro, United States

    2 weeks ago

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    Description

    Title: Sr. Mixed Signal Verification Engineer

    Location: Hillsboro, OR (hybrid)

    Duration: Full time / Direct hire

    Read the overview of this opportunity to understand what skills, including and relevant soft skills and software package proficiencies, are required.

    **Must be authorized to work in the U.S. - Visa support available via H1 transfer only.**

    Our client, a leader in the test-and-measurement, wireless communications, and cyber-security industries, has an immediate need for a highly motivated Mixed Signal Verification Engineer to join their team in designing the next generation data convertors for their world class test equipment. This is a small team environment in a great location that is very collaborative with close personal interactions. The selected individual will work with a highly qualified team of engineers, located both locally and abroad.

    Your Role

    You would be joining our client's elite team of world class data convertor designers. Your tasks would cover the entire spectrum of mixed signal verification of devices starting from conceptual, through design, layout, and characterization of the devices.

    As a key member of the team, your work will help to verify the function and performance of the designs. Verification activities range from leaf-cells, to top-level, to chip-to-chip interactions. The verification work will cover mixed signal components, both analog (> 30 GHz) and complex digital blocksacross the entire system.

    This is what you need to be selected:

    • Master's Degree in EE or ECE. Candidates with an EE or ECE Bachelor's degree and 4+ years of experience will also be considered.
    • More than 2 years of experience with an Analog Verification Flow (e.g. Cadence Virtuoso, Xcelium, AMS-Designer, Verilog-AMS, and Spectre).
    • Experience with SerDes is required
    • We will consider digital verification engineers with 4+ years of UVM experience that are interested in mixed signal verification.
    • Experience with modeling languages: Verilog-A, Verilog-AMS, SystemVerilog, UVM.
    • Experience creating mixed-signal self-checking test benches for automatic regression testing.
    • Comfortable working across analog and digital design paradigms.
    • General understanding of analog circuits and the ability to create analog behavioral models.
    • Self-driven, able to work independently while coordinating with analog and digital block designers
    • Strong scripting skills for working across analog / digital tools boundaries, such as Matlab, Python, Perl and make.
    • Ability to communicate effectively with both team members and external partners.
    • Ability to travel occasionally to European and U.S. locations.
    • Work effectively in a group setting (share expertise, provide and receive feedback, communicate technical issues, work in a team environment to resolve technical issues).

    Desirable qualifications - The more of these that you have, the better fit within the team:

    • Experience working in a mixed signal design environment.
    • Experience with system level design tools (e.g. Matlab, etc.).
    • Experience with scripting languages such as TCL, bash/tcsh, etc.
    • Experience verifying ASICs utilizing power gating and with multiple clock and power domains.
    • Experience with FPGA verification and board-level SERDES interface modelling.
    • Experience with fixed point DSP verification.
    • Experience with digitally assisted analog or controlled calibration of analog circuits.
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